UGC NET CS 2018 July - II Question 54

Question 54

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54. Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O ?

1. (1) I/O protection is ensured by operating system routines.
2. (2) I/O protection is ensured by a hardware trap.
3. (3) I/O protection is ensured during system configuration.
4. (4) I/O protection is not possible.

Answer: (1) I/O protection is ensured by operating system routines.

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UGC NET CS 2018 July - II Question 53	UGC NET CS 2018 July - II Question 55

UGC NET Computer Science July 2018 - II Question 53

Question 53

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53. In a multi-user operating system, 30 requests are made to use a particular resource per hour, on an average. The probability that no requests are made in 40 minutes, when arrival pattern is a poisson distribution, is ______ .

1. (1) e^-15
2. (2) 1 - e^-15
3. (3) 1 - e^-20
4. (4) e^-20

Answer : (4) e^-20

Explanation Question 53

In 1 Hour = 30 Requests Sent
∴ In 60 minutes = 30 Requests Sent
So, in 40 minutes = (30 x 40) / 60 = 20 Requests Sent

Here 20 is Number of request Sent in 40 minutes.
Let λ is number of request in 40 minutes
∴ λ = 20

But according to given statement in question Actual requests are made in 40 minutes is ZERO.

Let x is actual requests in 40 minutes.
i.e. x = 0 (According to Question)

As arrival pattern is a poisson distribution,
So, Probablity ( x ) = ( e^-λ * λ^x ) / x !
∴ Probablity ( x = 0 ) = ( e^-20 * λ⁰ ) / 0!
∴ Probablity ( x = 0 ) = e^-20

So, option (4) is correct answer.

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UGC NET CS 2018 July - II Question 52	UGC NET CS 2018 July - II Question 54

UGC NET Computer Science July 2018 - II Question 52

Question 52

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52. In a paged memory, the page hit ratio is 0.40. The time required to access a page in secondary memory is equal to 120 ns. The time required to access a page in primary memory is 15 ns. The average time required to access a page is ______ .

1. (1) 105
2. (2) 68
3. (3) 75
4. (4) 78

Answer : (4) 78

Explanation Question 52

PAGE HIT = page present in ram or main memory
PAGE MISS = page fault so page swapped from the secondary memory
because we look for a page in secondary memory when the page is not present in the main memory, therefore, we need to add main memory lookup time.

Average access time
= hit ratio * primary memory access time + (1 – hit ratio) * secondary memory access time
Average access time = 0.4 * 15 + 0.6 * 120
Average access time = 6 + 72
Average access time = 78.

So, option (4) is correct answer.

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UGC NET CS 2018 July - II Question 51	UGC NET CS 2018 July - II Question 53

UGC NET Computer Science July 2018 - II Question 51

Question 51

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51. At a particular time of computation, the value of a counting semaphore is 10. Then 12 P operations and “x” V operations were performed on this semaphore. If the final value of semaphore is 7, x will be :

Options:

1. (1) 8
2. (2) 9
3. (3) 10
4. (4) 11

Answer : (2) 9

Explanation Question 51

Intially the value of a counting semaphore is 10 Now 12 P operation are performed.

Now counting semaphore value = -2

“x” V operations were performed on this semaphore

Final value of counting semaphore = 7
∴ ( “x” V operations + current counting semaphore value (-2) ) = 7
∴ x + (-2) = 7
∴ x = 7 + 2
∴ x = 9.

So, option (2) is correct answer.

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UGC NET CS 2018 July - II Question 50	UGC NET CS 2018 July - II Question 52

UGC NET CS 2018 July - II Question 97

Question 97

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97. Match the items in List - I and List - II :

List - I	List -II
(a) Interrupts which can be delayed when a much highest priority interrupt has occurred	(i) Normal
(b) Unplanned interrupts which occur while executing a program	(ii) Synchronous
(c) Source of interrupt is in phase with the system clock	(iii) Maskable
	(iv) Exception

Code :

	(a)	(b)	(c)
(1)	(ii)	(i)	(iv)
(2)	(ii)	(iv)	(iii)
(3)	(iii)	(i)	(ii)
(4)	(iii)	(iv)	(ii)

Options:

1. (1)
2. (2)
3. (3)
4. (4)

Answer : (4)

Explanation Question 97

• (a) Interrupts which can be delayed when a much highest priority interrupt has occurred → (iii) Maskable
• (b) Unplanned interrupts which occur while executing a program → (iv) Exception
• (c) Source of interrupt is in phase with the system clock → (ii) Synchronous

→ Maskable Interrupt: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor.

→ Exception: unplanned interrupts while executing a program is called Exception. For example: while executing a program if we got a value which should be divided by zero is called a exception

Reference : Types of Interrupts

→ Synchronous interrupt will happen every time an instruction executes (with a given program state)
Examples of Synchronous interrupt:
– Divide by zero
– System call
– Bad pointer dereference

Reference 2 : Two types of interrupts - Synchronous / Asynchronous

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UGC NET CS 2018 July - II Question 96	UGC NET CS 2018 July - II Question 98

UGC NET CS 2018 July - II Question 95

Question 95

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95. The hexadecimal equivalent of the binary integer number 110101101 is :

1. (1) D24
2. (2) 1BD
3. (3) 1AE
4. (4) 1AD

Answer : (3) 1AE

Explanation Question 95

Answer: 3

Group the given number in subgroup of 4 from right and assign alphabet when it exceeds 1001:
1010 – A
1011 – B
1100 – C
1101 – D
1110 – E
1111 – F
Given number is 110101101:
1101 – D
1010 – A
1 – 1

Hexadecimal equivalent iss 1AD.
So, option (D) is correct.

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UGC NET CS 2018 July - II Question 94	UGC NET CS 2018 July - II Question 96

UGC NET CS 2018 July - II Question 90

Question 90

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Which of the following statements is true ?

1. (1) (Z, ≤ ) is not totally ordered
2. (2) The set inclusion relation ⊆ is a partial ordering on the power set of a set S
3. (3) (Z, ≠ ) is a poset
4. (4) The directed graph is not a partial order
   

   

   Diagram for option (4) The directed graph is not a partial order

Answer : (2) The set inclusion relation ⊆ is a partial ordering on the power set of a set S

Explanation Question 90

Options (1) - FALSE
(Z, ≤ ) is not totally ordered
Z = (..., -3, -2, -1, 0, 1, 2, 3, ...}
Show that “less than or equal” relation
is a partial ordering on the set of integers.
– a<=a for every integer a (reflexive)
– a<=b, b<=a, then a=b (anti-symmetric)
– a<=b, b<=c, then a<=c (transitive)
Thus <= is a partial ordering on the set of
integers
(Z,<=) is a poset.

To prove that Z is Totally Ordered Set:
If (S,R) is a poset and every two
elements of S are comparable, S is called
a totally ordered set or linearly ordered
set.

Comparable: The elements a and b of a poset (Z, ≤ )
are comparable, if either aRb or bRa holds.

Option 2: - TRUE
The set inclusion relation ⊆ is a partial ordering on the power set of a set S (TRUE)
let set S = {a,b}
P(S) = {{a} , {b} ,{a,b} , Φ}

Show that  relation (S,⊆) is a partial ordering on the set of integers.
Take any two element from S, lets say s1 and s2
– s1⊆s1 for every element s1 (reflexive)
– s1⊆s2, s2⊆s1, then s1==s2 (anti-symmetric)
– s1⊆s2, s2⊆s3, then s1⊆s3 (transitive)
Thus ⊆ is a partial ordering on the power set of a set S
(S,⊆) is a poset.

Options 3: - FALSE
(Z,≠) is a poset?
Show that (Z,≠) is a partial ordering on the set of integers.
Take any two integers, then
– aRa -> a≠a for every integer a (not reflexive)
Reflexive Relation doesn't satisfy.
So, (Z,≠) is not a poset.

Options 4: - FALSE
Relation set for the directed graph is D={(a,a),(a,b),(b,b)}
Reflecxive,transitive property holds for the elements in the set.
Anti-symattric -> if R(a, b) with a ≠ b, then R(b, a) must not hold, so, Anti-symattric also holds.

References:
Partial Orderings - http://cse.iitkgp.ac.in/~debdeep/courses_iitkgp/FOC/slidespdf/POS.pdf
Partially ordered set - https://en.wikipedia.org/wiki/Partially_ordered_set
Total order - https://en.wikipedia.org/wiki/Total_order

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UGC NET CS 2018 July - II Question 89	UGC NET CS 2018 July - II Question 91

UGC NET CS 2018 July - II Question 77

Question 77

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77. Consider the following English sentence :
"Agra and Gwalior are both in India".
A student has written a logical sentence for the above English sentence in First-Order Logic using predicate In(x, y), which means x is in y, as follows :
In(Agra, India) ∨ In(Gwalior, India)
Which one of the following is correct with respect to the above logical sentence ?

Options:

1. (1) It is syntactically valid but does not express the meaning of the English sentence.
2. (2) It is syntactically valid and expresses the meaning of the English sentence also.
3. (3) It is syntactically invalid but expresses the meaning of the English sentence.
4. (4) It is syntactically invalid and does not express the meaning of the English sentence.

Answer : (1) It is syntactically valid but does not express the meaning of the English sentence.

Explanation Question 77

Predicate In(Agra, India) means Agra is in india
Predicate In(Gwalior, India) means Gwalior is in india

According to the given english statement "Agra and Gwalior are both in India", both Predicate "In(Agra,India)" and "In(Gwalior,India)" should be true

Therefore use of conjunction as connector requires between both predicates "In(Agra, India) ∧ In(Gwalior, India)".

But given that In(Agra, India) ∨ In(Gwalior, India), in this it uses connector "∨". So, the entire gives the meaning of Either Agra is in india or Gwalior is in india.

So, Logic is not equivalent for given English sentence and given First-Order Logic.
Given predicate "In(Agra, India) ∨ In(Gwalior, India)" is syntactically correct but not represent the given english statement.

So, option 1 is correct answer

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UGC NET CS 2018 July - II Question 76	UGC NET CS 2018 July - II Question 78

UGC NET Computer Science July 2018 - II | Question 76

Question 76

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76. Consider the following statements :
(a) False ⊨ True
(b) If α ⊨ (β ∧ γ) then α ⊨ β and α ⊨ γ.
Which of the following is correct with respect to the above statements ?

1. (1) Both statement (a) and statement (b) are false.
2. (2) Statement (a) is true but statement (b) is false.
3. (3) Statement (a) is false but statement (b) is true.
4. (4) Both statement (a) and statement (b) are true.

Answer : (4) Both statement (a) and statement (b) are true.

Explanation Question 76

• Statement (a) "False ⊨ True" is TRUE
  A ⊨ B means "A" logically entails "B" if and only if the sentence A ⇒ B is valid.
  We need to prove that False ⇒ True is valid.
  ∴ False ⇒ True is always true
  because we know : (a ⇒ b) ≡ (¬a ∨ b) So, False ⇒ True is equivalent to ( ¬Flase ∨ True ) which is always true.
   
  
• Statement (b) "if α ⊨ (β ∧ γ) then α ⊨ β and α ⊨ γ" is TRUE
  by constructing below truth table you will find out that
  " α ⊨ β and α ⊨ γ " are true for all the cases for which "α ⊨ (β and γ)" is true
   
  

  α	β	γ	(β ∧ γ)	α ⊨ (β ∧ γ)	α ⊨ β	α ⊨ γ
  				¬ α ∨ (β ∧ γ)	¬ α ∨ β	¬ α ∨ γ
  0	0	0	0	1	1	1
  0	0	1	0	1	1	1
  0	1	0	0	1	1	1
  0	1	1	1	1	1	1
  1	0	0	0	0	0	0
  1	0	1	0	0	0	1
  1	1	0	0	0	1	0
  1	1	1	1	1	1	1

Definition of Logical Entailment
A set of sentences (called premises) logically entails a sentence (called a conclusion) if and only if every truth assignment that satisfies the premises also satisfies the conclusion.

Example of Logical Entailment:
“KB logically entails S” if all the models that evaluate KB to True also evaluate S to True.
Denoted by: KB ⊨ S

Reference : Logical Entailment

Reference 1 : Realm world example of Logical Entailment

Reference 2 : https://www.ics.uci.edu/~welling/teaching/271fall09/HW6_sol.pdf#page=8

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UGC NET CS 2018 July - II Question 75	UGC NET CS 2018 July - II Question 77

UGC NET CS 2018 July - II Question 94

Question 94

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94. What does the following logic diagram represent ?

Flip-Flop Logic diagram

Options:

1. 1. Synchronous Counter
2. 2. Ripple Counter
3. 3. Combinational Circuit
4. 4. Mod 2 Counter

Answer : 2. Ripple Counter

Explanation Question 94

Ripple Counter : Ripple counter is an Asynchronous counter. It got its name because the clock pulse ripples through the circuit. An n-MOD ripple counter contains n number of flip-flops and the circuit can count up to 2 ⁿ values before it resets itself to the initial value.

Given Flip-Flop Logic diagram represents the Ripple counter.

So, option 2 is correct answer

Reference : A Brief about Ripple Counter with Circuit and Timing Diagrams

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UGC NET CS 2018 July - II Question 93	UGC NET CS 2018 July - II Question 95